1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly relates to a method for forming a semiconductor element on a Silicon On Insulator (referred to as “SOI” hereinafter) substrate.
This application is a counterpart application of Japanese application Serial Number 205125/2000, filed on Jul. 6, 2000, the subject matter of which is incorporated herein by reference.
2. Prior Art
Recently, in the manufacture of semiconductor devices, it has become one of subject technical requirements to obtain semiconductor devices with ultra high speed performance and low electric power consumption. In order to comply with such a technical requirement, there has been proposed a technique for forming a large scale integrated circuit (referred to as “LSI” hereinafter) on the SOI wafer. For instance, as shown in FIG. 6e of the accompanying drawings, there is formed on the SOI wafer 12 a prior art semiconductor device 10 having a field effect transistor (referred to as “FET” hereinafter) of the metal oxide semiconductor (referred to as “MOS” hereinafter) type, according to the manufacturing steps as described in the following. FIGS. 6a to 6e of the accompanying drawings are schematic cross sectional illustrations of the prior art semiconductor device 10 for use in explanation of the prior art manufacturing steps thereof. FIGS. 7a and 7b of the same are also schematic cross-sectional illustrations of the semiconductor device 10 for use in explanation of the state of the semiconductor device 10 under the ion implantation process.
As shown in FIG. 6a, the SOI wafer 12 includes a buried oxide (referred to as “BOX” hereinafter) layer 16 stacked on a semiconductor substrate 14 and a semiconductor layer 18. To begin with, a field oxide film 20 is formed on the semiconductor layer 18, thereby insulating the semiconductor layer 18 with the BOX layer 16 and the field oxide film 20. Then, as shown in FIG. 6b, a gate oxide film 22 is formed on the semiconductor layer 18. Furthermore, as shown in FIG. 6c, channel ions of a medium dose amount are implanted in the interface between the semiconductor layer 18 and the gate oxide film 22. Still further, as shown in FIG. 6d, a source/drain region 28 is formed in the semiconductor layer 18 after forming a gate electrode 26 on the gate oxide film 22. Finally, an FET of the MOS type (referred to as “MOSFET” hereinafter) is completed by forming a inter-layer insulating film 30, contact holes 32, buried plugs 34, and a wiring layer 36. In the MOSFET formed on the SOI wafer 12, the channel region and the source/drain region 28 are formed on the BOX layer 16. Therefore, an LSI of the low power consumption type can be achieved without forming any depletion layer in the semiconductor substrate 14.
In the prior art semiconductor device 10, however, it has been experienced that the gate oxide film 22 is damaged or destroyed in the process of the channel ion implantation as shown in FIG. 6c. According to the knowledge of the inventor of this application, there is a relation among the dose amount of ion (B+) 24 (I), the damage occurrence percentage of gate oxide film 22 (II), and the charge-up potential difference of semiconductor layer 18 (III) as shown in the following Table 1.
TABLE 1the damagecharge-up potentialoccurrence percentagedifference of thedose amount of ionof gate oxide filmsemiconductor layer(ion/cm2)(%/mm2)(V)2 × 1012010.74 × 1012about 421.48 × 1012about 742.89 × 101230 to 3548.0
As will be seen from Table 1, the charge-up potential difference of the semiconductor layer 18 rises in response to the increase in the dose amount of the ion 24. Generally, if the SOI wafer 12 is formed by means of the Separation by Implanted Oxygen (referred to as “SIMOX” hereinafter) method, it is said that the dielectric withstanding voltage of the BOX layer 16 has a value in the voltage range of 40V to 60V. Therefore, if the charge-up potential difference of the semiconductor layer 18 is increased to approach a value of the dielectric withstanding voltage of the BOX layer 16, the damage occurrence rate (%) in the gate oxide film 22 is increased, accordingly. In the present specification, a term “dielectric withstanding voltage” is defined as an upper limit voltage at which a predetermined insulating layer may withstand without receiving any damage.
As described above, the semiconductor layer 18 is insulated with the BOX layer 16 and the gate oxide film 22 as well. Because of this, if ions 24 are implanted in the interface between the semiconductor layer 18 and the gate oxide film 22, the electric charge (+) 38 of the implanted ion 24 is charged up in the semiconductor layer 18 as shown in FIG. 7a. Furthermore, as shown in FIG. 7b, if the amount of the electric charge of the ion 24 in the semiconductor layer 18 is increased up to the level exceeding the value of the dielectric withstanding voltage of the BOX layer 16, a penetration path 40 is formed at a weak spot of the BOX layer 16, and the electron (−) 42 existing in the semiconductor substrate 14 is introduced into the gate oxide film 22 through the penetration path 40 and the semiconductor layer 18. As a result, the electron 42 comes to give a damage to the gate oxide film 22, thereby insulation failure, Time Dependence Dielectric Breakdown (referred to as “TDDB” hereinafter) or other similar defects being caused.
If the ion implantation for the Vt control (threshold value adjustment) is executed by means of a high dose ion implanter provided with an electron gun, the damage of the gate oxide film 22 might be considerably suppressed since there is hardly occurred the charge-up of the electric charge in the semiconductor layer 18. Generally speaking, however, the high dose ion implanter is designed for executing the ion implantation with the ion dose amount of 1×1014 ions/cm2 or more. Accordingly, if ion implantation with the ion dose amount of 2×1012 ions/cm2 to 1×1013 ions/cm2 is required, for instance like the case of forming the MOSFET on the SOI wafer 12, the control of the electric charge as charged up in the semiconductor layer 18 is apt to lose its uniformity, so that it becomes difficult to maintain the constant quality of the MOSFET in the manufacturing process thereof.
Still further, a report entitled “Gate Destruction by Charging Damage in Contact Etching” (TECHNICAL REPORT OF IEICE, SDM98-218 (1999–03)) points out the following problem with regard to the SOI wafer 12 on which the field oxide film 20 is formed by using the method for local oxidation of silicon (LOCOS) as shown in FIG. 6a. That is, as shown in FIG. 6e, in case of forming a contact hole 32 by the dry etching method, if the ion of halogen gas or fluorocarbon gas having the electric charge as an etchant (gas) reaches the semiconductor layer 18, the electric charge 38 is charged up in the semiconductor layer 18. As described above, this charge-up of the electric charge 38 in the semiconductor layer 18 takes place as the semiconductor layer 18 is insulated by the BOX layer 16 and the field oxide film 20 as well. If the thickness of the BOX layer 16 has a value in the thickness range of 100 nm to 120 nm, the dielectric withstanding voltage of the BOX layer 16 has a value in the voltage range of 40V to 50V, and if the charge-up potential derived from the electric charge of the etching gas ion exceeds the dielectric withstanding voltage, the permanent dielectric breakdown of the BOX layer 16 takes place and the dielectric breakdown of the gate oxide film 22 also takes place at the same time.